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a s3 5 6 0 cl a ss - g s te r e o h e a d p h o n e a m p l i f i e r www.austriamicrosystems.com/as3560 revision 1.03 1 19 d a t a s h e e t 1 general description the as3560 is a classg stereo headphone amplifier optimized for usage within portable devices. the classg supply r ail adaptation is implemented by an integrated dcdc buck converter th at takes its input directly from the battery. the continuous ado ption of supply rails is done according to the input signal swing a nd load conditions. this architecture implements significant power savi ngs compared to traditional classab amplifiers. an i2c control interface is implemented for a 32st ep volume control including a mute function for each channel separate ly. the integrated charge pump generates a symmetric ne gative supply for true ground output signal levels without the ne ed of output coupling capacitors. in addition it helps to lower the overall pop noise of the amplifier. a supervisory circuit is included for overtemperatu re and shortcircuit protection. differential inputs together with output ground sen sing guarantees very low noise sensitivity. figure 1. as3560 block diagram 2 key features gclass amplifier with integrated dcdc buck convert er 2x30mw, 0.02% thd @16 w >100db snr @0.9v rms popless startup and mute/unmute feature charge pump for true ground output without coupling capacitors direct battery connection with wide supply range: 2 .3v to 5.5v low power consumption optimized for battery operati on 1 ma quiescent current with both channels enabled <5 a shutdown current fully differential inputs reduce system noise also configurable as singleended inputs sgnd pin for ground sensing and ground feedback min imizes sensitivity to interference i2c control interface volume control with 32 gain steps, 59 to +4db, < 80db mute channel independent enable control current and temperature supervisor package: 0.4 mm pitch wlcsp (1.615x1.615mm) 3 applications mobile phones portable navigation devices, media devices media devices
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www.austriamicrosystems.com/as3560 revision 1.03 2 19 as3560 data sheet c o n t e n t s contents 1 general description ................................................... ................................................... ................................................... ......... 1 2 key features ................................................... ................................................... ................................................... ................... 1 3 applications ................................................... ................................................... ................................................... ..................... 1 4 pin assignments ................................................... ................................................... ................................................... .............. 3 4.1 pin descriptions ................................................... ................................................... ................................................... .......................... 3 5 absolute maximum ratings ................................................... ................................................... ................................................ 4 6 electrical characteristics ................................................... ................................................... ................................................... . 5 7 detailed operating characteristics ................................................... ................................................... ..................................... 7 8 detailed description ................................................... ................................................... ................................................... ........ 8 8.1 i2c control interface ................................................... ................................................... ................................................... ................... 8 9 register definition ................................................... ................................................... ................................................... ........... 9 9.1 register overview ................................................... ................................................... ................................................... ....................... 9 9.2 detailed register descriptions ................................................... ................................................... ................................................... .... 9 10 application information ................................................... ................................................... ................................................... .11 10.1 gnd connections ................................................... ................................................... ................................................... ................... 11 10.2 external elements ................................................... ................................................... ................................................... ................... 11 10.3 software shutdown ................................................... ................................................... ................................................... ................. 11 11 package drawings and markings ................................................... ................................................... ................................... 12 12 ordering information ................................................... ................................................... ................................................... .... 14
www.austriamicrosystems.com/as3560 revision 1.03 3 19 as3560 data sheet p i n a s s i g n m e n t s 4 pin assignments figure 2. pin assignments (top view) 4.1 pin descriptions table 1. pin descriptions pin name pin number description sw a1 buck converter switching node avdd a2 primary power supply for device hpl a3 left channel headphone amplifier output inln a4 inverting left input for differential signals; connect to left input signal through 2.2f capacito r for singleended input applications agnd b1 main ground for headphone amplifiers, dc/dc convert er, and charge pump cpp b2 charge pump positive flying cap; connect to 2.2f f lying capacitor hpvdd b3 power supply for headphone amplifier (dc/dc output node) inlp b4 noninverting left input for differential signals; connect to ground through 2.2f capacitor for singl eended input applications cpn c1 charge pump negative flying cap; connect to 2.2f f lying capacitor hpvss c2 charge pump output; connect 2.2f capacitor to gnd sgnd c3 ground sense; connect to headphone jack ground inrp c4 noninverting right input for differential signals; connect to right input signal through 2.2f capacit or for singleended input applications sda d1 i2c data; 1.8v logic compliant scl d2 i2c clock; 1.8v logic compliant hpr d3 right channel headphone amplifier output inrn d4 inverting right input for differential signals; connect to ground through 2.2f capacitor for singl eended input applications a1 sw a2 a3 a4 avdd sw hpl inln b1 agnd b2 b3 b4 cpp hpvdd inlp c1 cpn c2 c3 c4 hpvss sgnd inrp d1 sda d2 d3 d4 scl hpr inrn top view i2c inrp inrn inlp inln scl sda supervisor (current & temp) hpl hpr sgnd charge pump dcdc buck avdd hpvdd hpvss sw ground sense cpp cpn agnd as3560
www.austriamicrosystems.com/as3560 revision 1.03 4 19 as3560 data sheet a b s o l u t e m a x i m u m r a t i n g s 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these ar e stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in operating conditions on page 5 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . table 2. absolute maximum ratings parameter min max units comments supply voltage, avdd 0.3 7 v for 1 ms peaks amplifier supply voltage, hpvdd 0.3 2.0 v sgnd 0.3 0.3 v differential input voltage hpvss 0.3v hpvdd +0.3v v input voltage at scl, sda 0.3 7.0 v breakdown voltage at amplifier outputs hpvss 0.5 hpvdd +0.5 v input current (latchup immunity) 200 ma norm: jedec 7 8 continuous power dissipation continuous power dissipation tbd mw p t 1 1. depending on actual pcb layout and pcb used continuous power dissipation derating factor tbd mw/o c p derate 2 2. p derate derating factor changes the total continuous power dissipation (p t ) if the ambient temperature is not 70 o c. therefore for e.g. tamb=85 o c calculate p t at 85oc = p t p derate * (85 o c 70oc) electrostatic discharge esd hbm 2 kv norm: mil 883 e method 3015 esd mm 100 v norm: jedec jesd 22a115a level a esd cdm 500 v norm: jedec jesd 22c101c temperature range and storage conditions junction temperature +150 oc internally limited (overtemperature protection) auto shutdown at 140 oc storage temperature range 55 +125 oc package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/jedec jstd020moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices. humidity noncondensing 5 85 % moisture sensitive level 1 represents a max. floor li fe time of unlimited
www.austriamicrosystems.com/as3560 revision 1.03 5 19 as3560 data sheet e l e c t r i c a l c h a r a c t e r i s t i c s 6 electrical characteristics avdd=3.6v, t a =25 oc, rload = 32 w unless otherwise specified. table 3. operating conditions symbol parameter conditions min typ max units general operating conditions avdd supply voltage 2.3 5.5 v rail voltages hpvdd, hpvss (buck and cp output) 0.8 0.9 1.0 v 1.15 1.25 1.35 v 1.7 1.8 1.9 v i dd quiescent current both channels enabled, no audio signal 1.1 1.5 ma i sd shutdown current sw shutdown 1 5 ua i s supply current output: 2x100w @ 3db crest factor 2.0 3.5 ma output: 2x500w @ 3db crest factor 3.1 5.5 ma output: 2x1mw @ 3db crest factor 4.0 7.5 ma t a operating temperature range 30 25 +85 oc t wakeup wakeup time 10 15 ms input interfaces v il lowlevel input voltage (scl, sda) avdd 2.9v to 4.5v 0.6 v v ih highlevel input voltage (scl, sda) avdd 2.9v to 4.5v 1.2 v v hyst hysteresis (scl, sda) 50 100 200 mv z in input impedance line inputs differential 20 k w single ended 10 k w hpa output v out output voltage rload=16 w , thd+n=1%, l+r out of phase 0.7 v rms rload=32 w , thd+n=1%, l+r in phase 0.9 v rms output dc offset both channels enabled 500 v z out output impedance in hiz mode <40 khz 10 k w in hiz mode 6 mhz 500 w in hiz mode 36 mhz 75 w voltage applied to output; hpr, hpl when sws = 0, hiz_l = hiz_r = 1, device in hiz mode 1.8 1.8 v c load capacitive load ext. cap, 15 w series resistor 0.8 5 100 nf ext cap, directly connected 100 pf z oot,sd output impedance in shutdown sws = 1 8 k w voltage applied to output; hpr, hpl when sws = 1, de vice disabled 0.3 3.6 v audio parameters thd+n total harmonic distortion + noise 700mv rms , 1khz 0.01 0.02 % psrr power supply rejection ratio gain 0db @217 hz 90 db snr signaltonoise ratio 900mv rms , 1khz 104 db channel separation >16 w (headset) 60 db >10k w (lineout) 80 db
www.austriamicrosystems.com/as3560 revision 1.03 6 19 as3560 data sheet e l e c t r i c a l c h a r a c t e r i s t i c s v n output noise gain 0db, aweighted 5.3 9 v rms other parameters thermal shutdown threshold 140 oc hysteresis 20 table 3. operating conditions (continued) symbol parameter conditions min typ max units
www.austriamicrosystems.com/as3560 revision 1.03 7 - 19 as3560 data sheet - d e t a i l e d o p e r a t i n g c h a r a c t e r i s t i c s 7 detailed operating characteristics t a = 25oc, av dd (v dd ) = 3.6 v, gain = 0 db, c hpvdd = 10 uf, c hpvss = 2.2 f, c input = c flying = 2.2 f, rl=32 w unless otherwise specified. figure 3. thd+n versus output power for avdd=2.5v, rl=32 w figure 4. thd+n versus output power for avdd2.5 v, rl=16 w 0,001 0,01 0,1 1 10 0,1 1 10 100 pout (mw) thd+n [%] lef t ri ght 0,001 0,01 0,1 1 10 0,1 1 10 100 pout (mw) thd+n [%] lef t right figure 5. thd+n versus output power for avdd=3.6v, rl=32 w figure 6. thd+n versus output power for avdd= 3.6v, rl=16 w 0,001 0,01 0,1 1 10 0,1 1 10 100 pout (mw) thd+n [%] lef t right 0,001 0,01 0,1 1 10 0,1 1 10 100 pout (mw) thd+n [%] lef t right figure 7. thd+n versus output power for avdd=5.5v, rl=32 w figure 8. thd+n versus output power for avdd=5. 5v, rl=16 w 0,001 0,01 0,1 1 10 0,1 1 10 100 pout (mw) thd+n [%] lef t right 0,001 0,01 0,1 1 10 0,1 1 10 100 pout (mw) thd+n [%] lef t right
www.austriamicrosystems.com/as3560 revision 1.03 8 - 19 as3560 data sheet - d e t a i l e d o p e r a t i n g c h a r a c t e r i s t i c s figure 9. thd+n versus frequency for avdd=2.5v, r l=32 w figure 10. thd+n versus frequency for avdd=2.5 v, rl=16 w 0,0001 0,001 0,01 0,1 1 10 100 1000 10000 100000 f [hz] thd+n [%] 1mw 10mw 20mw 0,0001 0,001 0,01 0,1 1 10 100 1000 10000 100000 f [hz] thd+n [%] 1mw 10mw 20mw figure 11. thd+n versus frequency for avdd=3.6v, r l=32 w figure 12. thd+n versus frequency for avdd=3.6 v, rl=16 w 0,0001 0,001 0,01 0,1 1 10 100 1000 10000 100000 f [hz] thd+n [%] 1mw 10mw 20mw 0,0001 0,001 0,01 0,1 1 10 100 1000 10000 100000 f [hz] thd+n [%] 1mw 10mw 20mw figure 13. thd+n versus output power for avdd=5.5v , rl=32 w figure 14. thd+n versus output power for avdd= 5.5v, rl=16 w 0,0001 0,001 0,01 0,1 1 10 100 1000 10000 100000 f [hz] thd+n [%] 1mw 10mw 20mw 0,0001 0,001 0,01 0,1 1 10 100 1000 10000 100000 f [hz] thd+n [%] 1mw 10mw 20mw
www.austriamicrosystems.com/as3560 revision 1.03 9 - 19 as3560 data sheet - d e t a i l e d o p e r a t i n g c h a r a c t e r i s t i c s figure 15. supply current versus pout for avdd=2.5 v (pout is the output power per channel) figure 16. total power consumption vs. pout for av dd=2.5v (pout is the output power per channel) 1 10 100 0,1 1 10 100 pout (mw) i(avdd) [ma] 16 ohm 32 ohm 1 10 100 1000 0,1 1 10 100 pout (mw) ptotal [mw] 16 ohm 32 ohm figure 17. supply current versus pout for avdd=3.6 v (pout is the output power per channel) figure 18. total power consumption vs. pout for av dd=3.6v (pout is the output power per channel) 1 10 100 0,1 1 10 100 pout (mw) i(avdd) [ma] 16 ohm 32 ohm 1 10 100 1000 0,1 1 10 100 pout (mw) ptotal [mw] 16 ohm 32 ohm figure 19. supply current versus pout for avdd=5.5 v (pout is the output power per channel) figure 20. total power consumption vs. pout for a vdd=5.5v (pout is the output power per channel) 1 10 100 0,1 1 10 100 pout (mw) i(avdd) [ma] 16 ohm 32 ohm 1 10 100 1000 0,1 1 10 100 pout (mw) ptotal [mw] 16 ohm 32 ohm
www.austriamicrosystems.com/as3560 revision 1.03 10 - 19 as3560 data sheet - d e t a i l e d o p e r a t i n g c h a r a c t e r i s t i c s figure 21. quiescent current consumption versus av dd figure 22. psrr versus frequency (200mvpp su pply ripple) 0 0,5 1 1,5 2 2 3 4 5 avdd [v] i(avdd) [ma] audi o on audi o of f -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 f [hz] psrr [db] hpvdd figure 23. crosstalk versus frequency (700mvrms, r l= 32 w ) figure 24. startup pop noise for avdd=3.6v, rl =16 w -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 f [hz] crosstalk[db] 0 0,5 1 1,5 2 2,5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 t (ms) avdd [v] 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 headphone output [mv] avdd headphone output figure 25. startup pop noise for avdd=3.6v, rl=32 w 0 0,5 1 1,5 2 2,5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 t (ms) avdd [v] 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 headphone output [mv] avdd headphone output
www.austriamicrosystems.com/as3560 revision 1.03 11 19 as3560 data sheet d e t a i l e d d e s c r i p t i o n 8 detailed description 8.1 i2c control interface an i2c slave interface is implemented for read/writ e access of the internal registers. scl is the corr esponding clock input pin and sda the data input pin. access is done in 7bit addressing mode, addresses for read and write are defined by c0h = 11000000b ... write c1h = 11000001b ... read figure 26. i2c block diagram figure 27. i2c timing definition table 4. i2c timing parameters symbol parameter condition min typ max unit t sp spike insensitivity 50 100 ns t hi high clock time 400 khz clock speed 330 ns t lo low clock time 660 ns t su sda has to change tsetup before rising edge of sclk 30 ns t hd no hold time needed for sda relative to rising edge of cscl -40 ns t hd;sta within start condition, after low going sda, scl ha s to stay constant for the specified hold time 300 ns t su;sto after high going edge of scl, sda has to stay const ant for the specified setup time before stop or repeated start condition is applied 100 ns t su;sta 100 ns i2c interface scl sda registers 10k 10k as3560 t hd;sta t r t lo t hi t f t su;dat t su;sta t hd;sta t sp t su;sto stop start sr scl sda
www.austriamicrosystems.com/as3560 revision 1.03 12 19 as3560 data sheet r e g i s t e r d e f i n i t i o n 9 register definition 9.1 register overview 9.2 detailed register descriptions table 5. enable register (1h) table 6. volume register (2h) register description enable register (1h) general control register to switch on/off the devic e and enable the headphone amplifier stages. volume register (2h) allows the use to configure the output volume of th e headphone amplifier from 59db up to +4db. hiz register (3h) configures the headphone amplifier for a high imped ance output for power optimization. info register (4h) this register contains general information like ic version number and supplier information. bit bit name default access bit description bit 7 hp_en_l 0 rw 0 disable headphone left; 1 enable he adphone left channel bit 6 hp_en_r 0 rw 0 disable headphone right;1 enable he adphone right channel bit 5 bit 4 bit 3 bit 2 bit 1 thermal 0 s_rc 0 normal operation;1 thermal shutow n bit 0 sws 1 rw 0 normal operation;1 software shutdown bit bit name default access bit description bit 7 mute_l 1 rw 0 unmuted left channel;1 mute left cha nnel bit 6 mute_r 1 rw 0 unmuted right channel;1 mute right c hannel bit[5:1] vol[ 4:0] 0 rw 0d 59 db; 1d 55 db; 2d 51 db; 3d 47 db; 4d 43 db; 5d 39 db; 6d 35 db; 7d 31 db; 8d 27 db; 9d 25 db; 10d 23 db; 11d 21 db; 12d 19 db; 13d 17 db; 14d 15 db; 15d 13 db; 16d 11 db; 17d 10 db; 18d 9 db; 19d 8 db; 20d 7 db; 21d 6 db; 22d 5 db; 23d 4 db; 24d 3 db; 25d 2 db; 26d 1 db; 27d 0 db; 28d 1 db; 29d 2 db; 30d 3 db; 31d 4 db bit 0
www.austriamicrosystems.com/as3560 revision 1.03 13 19 as3560 data sheet r e g i s t e r d e f i n i t i o n table 7. hiz register (3h) table 8. info register (4h) bit bit name default access bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 hiz_l 0 rw 0 normal operation;1 high impedance on hph_output left bit 0 hiz_r 0 rw 0 normal operation;1 high impedance on hph_output right bit bit name default access bit description bit 7 supplier bit [1:0] ro 1 11b default supplier id; else unused bit 6 1 bit 5 bit 4 bit 3 version bit [3:0] ro 0 0 first version; else unused bit 2 0 bit 1 0 bit 0 0
www.austriamicrosystems.com/as3560 revision 1.03 14 19 as3560 data sheet a p p l i c a t i o n i n f o r m a t i o n 10 application information figure 28. as3560 application board 10.1 gnd connections the sgnd pin is an input reference and must be conn ected to the headphone ground connector pin. this e nsures no turnon pop and minimizes output offset voltage. do not connect more than 0. 3v to sgnd. agnd is a power ground. connect supply decoupling capacitors for avdd, hpvdd, and hpvss to agnd. 10.2 external elements 1 x 3.3 uh coil (swhpvdd) 7 x 2.2 uf 10% x5r (avdd, cppcpn, hpvss, inrp, in rn, inlp, inln) 1 x 10 uf 10% x5r (hpvdd) 10.3 software shutdown set software shutdown by writing a logic 1 in enable register (1h) , bit 0 (sws bit). software shutdown places the dev ice in the lowest power state. see operating conditions for values. engaging software shutdown turns off t he buck regulator and charge pump and disables the amplifier outputs. write a logic 0 to the sws bit to reactiva te the device. note: when the device is in sws mode all registers will m aintain their values. the hp_en_l and hp_en_r bits can be reset because a full word must be used when writing just one bit to the register. note that i2c read and write access is still possib le in shutdown mode. 1 1 2 2 3 3 4 4 d d c c b b a a title size date project title revision sheet of originator mtp as3560 application schematic v1.1 18.01.2010 4 3 a4 l1 3.3uh c1 10uf c2 2.2uf c4 2.2uf c3 2.2uf c5 2.2uf c6 2.2uf c7 2.2uf c8 2.2uf gnd scl sda avdd 3 1 2 l r gnd u3 headphone 3 1 2 l r gnd u4 input left 3 1 2 l r gnd u2 input right sw hpvdd cpp cpn hpvss hpl hpr sgnd scl sda inln inlp inrn inrp inrp_meas inrn_meas inln_meas inlp_meas d2 esd d3 esd d4 esd d5 esd d6 esd d7 esd t1 as3560 sw a1 avdd a2 hpl a3 inln a4 agnd b1 cpp b2 hpvdd b3 inlp b4 cpn c1 hpvss c2 sgnd c3 inrp c4 sda d1 scl d2 hpr d3 inrn d4 u1 as3560 as3560 eval board t2 3 1 2 l r gnd u5 stereo single ended j20 en. stereo right j19 en. stereo left d8 esd d9 esd t3 sgnd sgnd
www.austriamicrosystems.com/as3560 revision 1.03 15 19 as3560 data sheet p a c k a g e d r a w i n g s a n d m a r k i n g s 11 package drawings and markings figure 29. wl-csp (1.615x1.615mm) marking packaging code xxxx the device is available in a wlcsp (1.615x1.615mm) package. xxxx encoded datecode
www.austriamicrosystems.com/as3560 revision 1.03 16 19 as3560 data sheet p a c k a g e d r a w i n g s a n d m a r k i n g s figure 30. wlcsp (1.615x1.615mm) package
www.austriamicrosystems.com/as3560 revision 1.03 17 19 as3560 data sheet r e v i s i o n h i s t o r y revision history note: typos may not be explicitly mentioned under revisio n history. revision date owner description 0.01 sep 10 th , 2009 pkm initial draft template 0.02 sep 23 rd , 2009 wsg revised draft 0.04 sep 29 th , 2009 wsg after first review 0.06 feb 9 th , 2010 wsg update on detailed operating characteristics 0.07 sep 17 th , 2010 hgt updated operating characteristics and package dr awing 0.99 nov 23rd, 2010 hgt layout change of operating cha racteristic 1.01 dec 20th, 2010 hgt first official release 1.02 june 6th, 2011 hgt changed order information 1.03 june 27th, 2011 hgt changed order information
www.austriamicrosystems.com/as3560 revision 1.03 18 19 as3560 data sheet o r d e r i n g i n f o r m a t i o n 12 ordering information the devices are available as the standard products shown in table 9 . note: all products are rohs compliant and austriamicrosys tems green. buy our products or get free samples online at icdi rect: http://www.austriamicrosystems.com/icdirect for further information and requests, please contac t us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor table 9. ordering information ordering code description delivery form package as3560bwlt as3560 classg stereo headphone amplifie r tape&reel wlcsp 16
www.austriamicrosystems.com/as3560 revision 1.03 19 19 as3560 data sheet c o p y r i g h t s copyrights copyright ? 20092010, austriamicrosystems ag, tobe lbaderstrasse 30, 8141 unterpremstaetten, austriae urope. trademarks registered ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, o r used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective compa nies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisio ns appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent in fringement. austriamicrosystems ag reserves the rig ht to change specifications and prices at any time and without notice. therefore, prior to de signing this product into a system, it is necessary to check with austriamicrosystems ag for current information. this product is intended for u se in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliabi lity applications, such as military, medical lifes upport or lifesustaining equipment are specifically not recommended without additional pro cessing by austriamicrosystems ag for each applicat ion. for shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flo w or test location. the information furnished here by austriamicrosyste ms ag is believed to be correct and accurate. howev er, austriamicrosystems ag shall not be liable to recipient or any third party for any d amages, including but not limited to personal injur y, property damage, loss of profits, loss of use, interruption of business or indirect, special, inci dental or consequential damages, of any kind, in co nnection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or oth er services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives , please visit: http://www.austriamicrosystems.com/contact

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